Lead FPGA Design Engineer
- 职位编号
- J2456812
- 地点
- Austin, Texas, United States of America
- 类别
- 工程
- 发布日期
- 07/16/2026
- 工作时间类型
- 全职
在捷普(NYSE:JBL),我们很自豪能够成为世界顶级品牌值得信赖的合作伙伴,提供综合的工程、制造和供应链解决方案。凭借60年的跨行业经验和遍布全球的100多个工厂,捷普将全球覆盖影响力与当地专业知识相结合,提供可扩展和定制化的解决方案。我们的承诺超越商业成功,致力于构建可持续的流程,最大限度减少环境影响,并促进全球不同社区的繁荣与多样。
JOB SUMMARY
The FPGA Lead Engineer is responsible for leading FPGA design, development, integration, and debug activities for complex server, storage, networking, AI infrastructure, and rack-level platforms. This role provides technical ownership for FPGA architecture, RTL implementation, verification readiness, hardware bring-up, and cross-functional issue resolution to ensure programmable logic solutions meet system requirements, schedule commitments, manufacturability expectations, and customer quality targets.
ESSENTIAL DUTIES AND RESPONSIBILITIES
- Technical Leadership: Lead development teams, conduct design reviews, and oversee requirement traceability. Act as the technical liaison between cross-functional partners, system architects, and program managers.
- Hardware Validation: Lead debugging and testing campaigns on physical printed circuit boards (PCBs) using lab equipment like digital oscilloscopes, logic analyzers, and function generators.
- Project Management: Plan and manage technical, cost, and schedule objectives. Monitor technical risks and handle configuration.
- Own investigation and closure of complex FPGA, hardware, and firmware integration issues during bring-up, validation, manufacturing ramp, and customer escalation.
- Partner with Electrical, BIOS, BMC, Systems, Validation, Manufacturing, and customer teams to resolve cross-domain issues and align technical decisions.
- Support FPGA verification readiness, lab debug, hardware validation, and release criteria by ensuring requirements traceability and disciplined issue management.
- Mentor junior engineers and contribute to reusable design practices, coding standards, documentation quality, and engineering best practices.
- Communicate technical direction, risks, tradeoffs, milestone health, and resolution plans clearly to leadership, customers, and cross-functional stakeholders.
JOB QUALIFICATIONS
Education & Experience
- Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related technical field; Master’s degree preferred.
- 5–10 years of relevant experience in FPGA design, programmable logic development, hardware integration, or related platform engineering work.
Knowledge, Skills, and Abilities
- Strong expertise in FPGA design flows, RTL development, simulation, synthesis, timing analysis, constraints, and lab-based debug.
- Experience with common FPGA toolchains and devices from vendors such as AMD/Xilinx, Intel/Altera, or equivalent platforms is required. Strong understanding of standard digital interfaces like SPI, I2C, UART, Ethernet, PCIe, or JESD protocols
- Experience with server, storage, networking, accelerator, PCIe-based, or other complex compute platforms is preferred.
- Ability to lead technical decisions, drive root cause analysis, and align multiple engineering disciplines toward successful execution.
- Strong written and verbal communication skills, including the ability to explain complex programmable logic issues clearly to technical and non-technical stakeholders.
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Jabil, including its subsidiaries, is an equal opportunity employer and considers qualified applicants for employment without regard to race, color, religion, national origin, sex, age, disability, genetic information, veteran status, or any other characteristic protected by law.
Accommodation Statement
If you are a qualified individual with a disability, you have the right to request a reasonable accommodation if you are unable or limited in your ability to use or access Jabil.com/Careers site as a result of your disability. You can request a reasonable accommodation by sending an e-mail to Always_Accessible@Jabil.com or calling 727-803-7988 with the nature of your request and contact information. Please do not direct any other general employment related questions to this e-mail or phone number. Please note that only those inquiries concerning a request for reasonable accommodation will be responded to.
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